Automatic layout of scalable embedded field programmable gate array

This paper presents a layout technique for scalable embedded Field Programmable Gate Array architecture (eFPGA). It describes the total ?ow to generate a variety of eFPGA architectures using parameterized generators and Alliance CAD developed in the university of Paris6 We will show one example of realization using a symbolic library of cells. Our test eFPGA have a symmetric mesh architecture (Island-style) composed of ?ve main tiles. The scalability of this tiles can be varied to obtain the best design ?t on the System on Chip device.