SMART: a simulation tool for analyzing cache access behavior on SMPs

This paper presents SMART - a simulation tool for analyzing the cache access behavior on SMP systems. SMART traps memory access events of multi-threaded applications, simulates the accesses in multiple levels of caches of multiple processors and the shared memory, emulates a novel hardware monitor that records events within given address ranges of interest, and presents the result as event counts or histogram in arbitrary granularity. Used independently or together with the advanced tools developed in the EP-Cache project, SMART can help evaluate the performance of multi-threaded applications with different hardware configurations and facilitate the application of effective code transformations for optimization.