SNDR sensitivity analysis for cascaded ΣΔ modulators

Author

Morizio, James ; Hoke, Michael ; Kocak, Taskin ; Geddie, Clark ; Hughes, Chris ; Perry, John ; Madhavapeddi, Srinadh ; Hood, Michael ; Huffman, Ward ; Okuda, Takashi ; Noda, Hiroshi ; Morimoto, Yasuo ; Kumamoto, Toshio ; Ishiwaki, Masahiko ; Kondoh, Haruf

Author_Institution

Electron. Device Group, Mitsubishi Electron. America, Durham, NC, USA

Volume

3

fYear

2000

fDate

2000

Abstract

Cascade, single and multi-bit, ΣΔ architectures provide stable, high order quantization noise shaping used in high resolution A/D conversion. One major disadvantage of cascaded ΣΔ topologies is the extreme SNDR sensitivity to gain mismatch between the analog modulator and the digital error correction logic. This paper will investigate this SNDR sensitivity phenomenon for a 6th order, 1-bit quantizer and 4th order, 5-bit quantizer cascaded ΣΔ A/D system. Circuit parameters of the switched capacitor integrator such as amplifier open loop gain, integrator gain, and amplifier offsets and layout parasitics are characterized

Keywords

cascade networks; integrating circuits; network parameters; quantisation (signal); sensitivity analysis; sigma-delta modulation; switched capacitor networks; SNDR sensitivity analysis; amplifier offsets; amplifier open loop gain; analog modulator; cascaded sigma-delta modulators; circuit parameters; digital error correction logic; gain mismatch; high resolution A/D conversion; integrator gain; layout parasitics; quantization noise shaping; switched capacitor integrator; Capacitors; Circuits; Delta modulation; Error correction; Finite impulse response filter; Mathematical model; Noise shaping; Sensitivity analysis; Switches; Transfer functions;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.856172

Filename

856172