DocumentCode :
2229575
Title :
Repeater insertion in deep sub-micron CMOS: ramp-based analytical model and placement sensitivity analysis
Author :
Nalamalpu, Ankireddy ; Burleson, Wayne
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Volume :
3
fYear :
2000
fDate :
2000
Firstpage :
766
Abstract :
Repeaters are now widely used to increase the performance of long on-chip interconnections in CMOS VLSI. In this paper, we take an updated look at repeater insertion in state-of-the-art CMOS, using a new more detailed model. In spite of the more complex model, we present closed form expressions for the delay and the optimal repeater spacing and sizing. Our model is based on the alpha-power law to account for the short-channel effects and resistive loads that arise in deep sub-micron technologies. Unlike previous work, we model the repeater input as a ramp and accurately model both linear and saturation regions of operation for estimating the propagation delay. Our analytical repeater model is applied for estimating the performance of driving various repeated RC loads and exhibits a maximum error of only 5% when compared with SPICE in a 0.13 μm CMOS technology. In practice, it is not always feasible to insert the repeaters at the exact optimal locations along an interconnect. We present a placement sensitivity analysis to quantify the effect of the sub-optimal repeater placement on performance. Closed form expressions are derived to re-size the repeaters to compensate for the sub-optimal placement
Keywords :
CMOS integrated circuits; VLSI; circuit simulation; delays; integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; sensitivity analysis; 0.13 micron; VLSI; alpha-power law; closed form expressions; deep sub-micron CMOS; on-chip interconnections; optimal repeater spacing; placement sensitivity analysis; propagation delay; ramp-based analytical model; repeater insertion; resistive loads; saturation regions; short-channel effects; Analytical models; CMOS technology; Delay estimation; Performance analysis; Propagation delay; Repeaters; SPICE; Semiconductor device modeling; Sensitivity analysis; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
Type :
conf
DOI :
10.1109/ISCAS.2000.856173
Filename :
856173
Link To Document :
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