Title :
Efficient ROM size reduction for distributed arithmetic
Author :
Choi, Jung-Pal ; Shin, Seung- Cheol ; Chung, Jin- Gyun
Author_Institution :
Dept. of Inf. & Commun. Eng., Chonbuk Nat. Univ., Chonju, South Korea
Abstract :
In distributed arithmetic-based architecture for an inner product between two length N vectors, the size of the ROM increases exponentially with N. Moreover, the ROMs are generally the bottleneck of speed, especially when their size is large. In this paper, a ROM size reduction technique for DA (Distributed Arithmetic) is proposed. The proposed method is based on modified OBC (Offset Binary Coding) and a control circuit reduction technique. By simulations, it is shown that the use of the proposed technique can result in reduction in the number of gates by up 50%
Keywords :
circuit complexity; distributed arithmetic; encoding; integrated memory circuits; read-only storage; ROM size reduction; circuit complexity analysis; control circuit reduction technique; distributed arithmetic-based architecture; inner product; modified OBC; offset binary coding; Arithmetic; Circuit simulation; Computer architecture; Convolution; Discrete cosine transforms; Read only memory;
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
DOI :
10.1109/ISCAS.2000.856258
