DocumentCode
2230060
Title
Combined subthreshold and gate-oxide leakage power reduction in deep-submicron CMOS Circuits
Author
Guindi, Rafik S.
Author_Institution
Cairo University
fYear
2004
fDate
5-7 Sept. 2004
Firstpage
535
Lastpage
540
Keywords
CMOS logic circuits; CMOS technology; Clocks; Energy consumption; Leakage current; Power engineering and energy; Probability; State estimation; Subthreshold current; Tunneling;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical, Electronic and Computer Engineering, 2004. ICEEC '04. 2004 International Conference on
Print_ISBN
0-7803-8575-6
Type
conf
DOI
10.1109/ICEEC.2004.1374524
Filename
1374524
Link To Document