2230060

Combined subthreshold and gate-oxide leakage power reduction in deep-submicron CMOS Circuits

Guindi, Rafik S.

Cairo University

2004

5-7 Sept. 2004

535

540

CMOS logic circuits; CMOS technology; Clocks; Energy consumption; Leakage current; Power engineering and energy; Probability; State estimation; Subthreshold current; Tunneling;

English

ieee

Electrical, Electronic and Computer Engineering, 2004. ICEEC '04. 2004 International Conference on

0-7803-8575-6

conf

10.1109/ICEEC.2004.1374524

1374524