FVP: a formal verification platform for SoC

Author

Liao, WenShiu ; Hsiung, PaoAnn

Author_Institution

Dept. of Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Chiayi, Taiwan

fYear

2003

fDate

17-20 Sept. 2003

Firstpage

21

Lastpage

24

Abstract

How to verify a system-on-a-chip (SoC) has been an important issue in the SoC design process due to its complexity. The capacity of traditional verification techniques such as simulation or emulation is no longer suitable for SoCs. However, formal verification that provides 100% coverage and counterexamples is expected to be a complementary solution. Several researches on formally verifying an SoC have demonstrated its feasibility and benefits. Nevertheless, there is no utility for platform-based formal verification of SoCs as yet. A formal verification platform (FVP) is proposed to formally verify an intellectual property (IP) by providing a formal platform to create its environment. We illustrate our modeling experiences using the model checker SGM.

Keywords

formal verification; industrial property; integrated circuit design; integrated circuit modelling; logic design; system-on-chip; FVP; IP reuse; SoC formal verification platform; counterexamples; intellectual property; model checker; system-on-a-chip; verification coverage; Clocks; Computer science; Emulation; Explosions; Formal verification; Hardware; Intellectual property; Process design; State-space methods; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]

Print_ISBN

0-7803-8182-3

Type

conf

DOI

10.1109/SOC.2003.1241454

Filename

1241454