Independent clocks for peripheral modules in system-on-chip design

Author

Watn, Rune ; Njolstad, T. ; Berntsen, F. ; Lonnum, J.F.

Author_Institution

Dept. of Phys. Electron., Norwegian Univ. of Sci. & Technol., Trondheim, Norway

fYear

2003

fDate

17-20 Sept. 2003

Firstpage

25

Lastpage

28

Abstract

A robust solution for enabling the use of independent clocks for peripheral modules in system-on-chip design is proposed. By combining a standard synchronous on-chip bus architecture with GALS methodology, the advantage of a high-bandwidth low-latency system bus and independent clock domains for peripheral modules is achieved. The peripheral modules are still allowed to have continuous clocks and operate as in a standard synchronous environment. The solution is tested in an existing AMBA based simulation testbed, and correct behavioral functionality is confirmed.

Keywords

asynchronous circuits; clocks; logic design; logic simulation; system buses; system-on-chip; AMBA; GALS methodology; SOC; globally-asynchronous locally-synchronous design; high-bandwidth low-latency system bus; independent peripheral module clocks; synchronous on-chip bus architecture; system-on-chip design; Bridge circuits; Chip scale packaging; Clocks; Displays; Frequency conversion; Integrated circuit interconnections; System buses; System-on-a-chip; Testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]

Print_ISBN

0-7803-8182-3

Type

conf

DOI

10.1109/SOC.2003.1241455

Filename

1241455