DocumentCode :
2230139
Title :
Concurrent analysis techniques for data path timing optimization
Author :
Monahan, Chuck ; Brewer, Forrest
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
fYear :
1996
fDate :
3-7 Jun, 1996
Firstpage :
47
Lastpage :
50
Abstract :
Conventional High-level Synthesis techniques create an interconnection structure before physical design. Following physical design, connection delays and special requirements may cause the structure to fail timing or performance constraints. Alterations to this structure are often limited since it was created either after or during the binding and scheduling tasks. In this paper we present a set of techniques which analyze the timing trade-offs associated with the position-specific interconnection network given the freedom of high-level binding and rescheduling changes
Keywords :
circuit layout CAD; circuit optimisation; high level synthesis; integrated circuit interconnections; integrated circuit layout; logic CAD; timing; binding; concurrent analysis techniques; connection delays; conventional high-level synthesis techniques; data path timing optimization; high-level binding; interconnection structure; performance constraints; position-specific interconnection network; rescheduling changes; scheduling; Cost function; Data analysis; Degradation; Delay; Feedback; High level synthesis; Multiprocessor interconnection networks; Network synthesis; Permission; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference Proceedings 1996, 33rd
Conference_Location :
Las Vegas, NV
ISSN :
0738-100X
Print_ISBN :
0-7803-3294-6
Type :
conf
DOI :
10.1109/DAC.1996.545543
Filename :
545543
Link To Document :
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