Title :
An autonomous multiple module clock synchronization methodology for SoC
Author :
Mai, ShiDai ; Lune, HongWen ; Hsu, RenChien ; Su, Chauchin
Author_Institution :
Dept. of Electr. Eng., Nat. Central Univ., Chung-li, Taiwan
Abstract :
Global clock synchronization is achieved autonomously by (1) phase locking to a reference PN (pseudorandom noise) clock, (2) detecting the lead/lag for the neighbors, and (3) fine tuning its own phase according to the decision fed back from the neighbors. The chip has been implemented by the TSMC 0.35 μm 1P4M digital process. An evaluation board of 5 modules has been implemented and measured For an initial jitter of 200 ps and skew of 800 ps, the output jitter is 47 ps and skew is 100 ps after lock on in a PC board environment.
Keywords :
circuit feedback; clocks; integrated circuit design; integrated circuit measurement; logic design; logic simulation; phase detectors; phase locked loops; random sequences; synchronisation; system-on-chip; timing jitter; 0.35 micron; SoC; autonomous multiple module clock; circuit feedback; clock distribution; clock generation; clock output jitter; clock skew; global clock synchronization methodology; local phase locked loop; phase detector; phase fine tuning; pseudorandom noise clock; reference PN clock phase locking; Clocks; Delay; Detectors; Filters; Frequency synchronization; Jitter; Phase detection; Phase locked loops; Tiles; Voltage-controlled oscillators;
Conference_Titel :
SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]
Print_ISBN :
0-7803-8182-3
DOI :
10.1109/SOC.2003.1241458
