DocumentCode
2230213
Title
Improved Mitchell-based logarithmic multiplier for low-power DSP applications
Author
McLaren, Duncan J.
Author_Institution
Inst. for Syst. Level Integration, Livingston, UK
fYear
2003
fDate
17-20 Sept. 2003
Firstpage
53
Lastpage
56
Abstract
This paper presents a method to improve the accuracy of a logarithmic multiplier, based on Mitchell´s algorithms for calculating logarithms and antilogarithms. The method developed offers an area saving of approximately 50% and a power saving of 71% for larger input widths. A FIR filter based on the multiplier is also presented.
Keywords
FIR filters; digital arithmetic; logic design; low-power electronics; FIR filter; Mitchell-based logarithmic multiplier; antilogarithm calculation; logarithm calculation; low-power DSP applications; multiplier accuracy; Algorithm design and analysis; Clocks; Councils; Design engineering; Digital signal processing; Filters; Interpolation; Power engineering and energy; Signal processing algorithms; Table lookup;
fLanguage
English
Publisher
ieee
Conference_Titel
SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]
Print_ISBN
0-7803-8182-3
Type
conf
DOI
10.1109/SOC.2003.1241461
Filename
1241461
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