• DocumentCode
    2230298
  • Title

    Performance-Sensitivity-based Workload Tailoring for Effective Design Exploration

  • Author

    Luo, Jie ; Zhang, Yilin ; Vadlamani, Saarvaani ; Lee, Byeong Kil

  • Author_Institution
    Univ. of Texas at San Antonio, San Antonio, TX, USA
  • fYear
    2012
  • fDate
    16-18 April 2012
  • Firstpage
    496
  • Lastpage
    501
  • Abstract
    Early-stage design exploration requires the detailed simulation which is running applications on a cycle-level microprocessor simulator. Main objectives of simulation-level design exploration include understanding the architectural behaviors of target applications and finding optimal configurations to cover wide range of applications in terms of performance and power. However, full simulation of an industry standard benchmark suite (e.g., SPEC CPU 2006) takes several weeks to months to complete. This problem has motivated several research groups to come up with methodologies to reduce simulation time while maintaining a certain level of accuracy. Among many techniques for reducing simulation time, a tool called Sim Point is popularly used. However, simulation load even with the reduced workloads is still heavy, considering design complexity of modern microprocessors. Basic motivation of this research is started from how design exploration is actually performed. Designers will observe the performance impact from resource variations or configuration changes. If a simulation point shows low sensitivity to resource variations, designers would eliminate those simulation points from the simulation setup procedure. In this paper, we focus on identifying those simulation points which have high sensitivity or low sensitivity, by which overall simulation methodology can be effectively improved. We also performed the performance-sensitivity-based similarity analysis (grouping) among simulation points on specific performance metric which can be an overall performance metric or a component-level metric.
  • Keywords
    circuit simulation; microprocessor chips; performance evaluation; power aware computing; sensitivity analysis; SimPoint; architectural behaviors; component-level metric; cycle-level microprocessor simulator; design complexity; effective design exploration; performance metric; performance-sensitivity-based similarity analysis; performance-sensitivity-based workload tailoring; resource variations; simulation setup procedure; simulation time; simulation-level design exploration; standard benchmark suite; target applications; Benchmark testing; Hardware; Hidden Markov models; Mathematical model; Sensitivity; Standards; early-stage design exploration; performance evaluation; workload characterization; workload reduction;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Information Technology: New Generations (ITNG), 2012 Ninth International Conference on
  • Conference_Location
    Las Vegas, NV
  • Print_ISBN
    978-1-4673-0798-7
  • Type

    conf

  • DOI
    10.1109/ITNG.2012.112
  • Filename
    6209201