An automatic offset compensation technique applicable to existing operational amplifier core cell

Author

Kayal, M. ; Sáez, R. T L ; Declercq, M.

Author_Institution

Electron. Lab., Fed. Inst. of Technol., Lausanne, Switzerland

fYear

1998

fDate

11-14 May 1998

Firstpage

419

Lastpage

422

Abstract

An automatic offset compensation scheme for two-stage operational amplifiers is described. The presented technique can be applied to an existing OA core cell without modifying its design. Offset voltage is reduced by digitally adjusting the resulting offset current at the node between the first and second OA stages. A background calibration is achieved by using a ping-pong structure that improves the temperature stability and an on-demand calibration is also provided. The proposed circuit has been fabricated in a 0.7 μm digital CMOS technology. The measured input offset voltage of the test circuits are less than ±200 μV

Keywords

CMOS analogue integrated circuits; calibration; circuit stability; compensation; integrated circuit measurement; operational amplifiers; 0.7 micron; CMOS technology; automatic offset compensation technique; background calibration; input offset voltage; offset current; operational amplifier core cell; ping-pong structure; temperature stability; Application specific integrated circuits; Approximation algorithms; Clocks; Frequency; Joining processes; Noise cancellation; Operational amplifiers; Registers; Transconductance; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-4292-5

Type

conf

DOI

10.1109/CICC.1998.695010

Filename

695010