New in-place strategy for a mixed-radix FFT processor

Author

Heo, Kyung L. ; Baek, J.H. ; Sunwoo, Mpng H. ; Jo, Byung G. ; Son, Bpng S.

Author_Institution

Sch. of Electr. & Comput. Eng., Ajou Univ., Suwon, South Korea

fYear

2003

fDate

17-20 Sept. 2003

Firstpage

81

Lastpage

84

Abstract

This paper proposes a fast Fourier transform (FFT) processor using a new in-place strategy and the mixed-radix algorithm. The proposed processor uses only two N-word memories for a continuous flow FFT implementation, due to the new in-place strategy, while existing continuous FFT processors use four N-word memories. In addition, the proposed processor satisfies both small area and real-time processing requirement. The gate count of the processor is 37,000 and the number of clock cycles is 640 for a 512-point FFT. Hence, the proposed FFT processor can reduce the gate count and memory size compared with existing FFT processors.

Keywords

digital arithmetic; fast Fourier transforms; integrated circuit design; integrated memory circuits; logic design; microprocessor chips; real-time systems; FFT in-place strategy; N-word memories; continuous flow implementation; fast Fourier transform; gate count reduction; memory size reduction; mixed-radix FFT processor; real-time processing; Clocks; Computer architecture; Digital video broadcasting; Fast Fourier transforms; Flexible printed circuits; Frequency division multiplexing; Memory architecture; Modems; OFDM modulation; Wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]

Print_ISBN

0-7803-8182-3

Type

conf

DOI

10.1109/SOC.2003.1241467

Filename

1241467