Title :
An area and power efficient RAKE receiver architecture for DSSS systems
Author :
Lee, Hyung-Jin ; Ha, Dong Sam
Author_Institution :
Dept. of Electr. & Comput. Eng., Virginia Tech VLSI for Telecommun. Lab, Blacksburg, VA, USA
Abstract :
In this paper, an area and power efficient RAKE receiver architecture is proposed for base and mobile-stations employing the direct sequence spread spectrum (DSSS) technique. One common parallel de-spreader provides precomputed sub-symbols to fingers for the proposed design, and, hence, each finger can operate at a lower clock speed to save power. Our simulation results indicate that the proposed RAKE architecture for a WCDMA system reduces power dissipation by 37% and the circuit complexity by 28% compared with that of a conventional RAKE receiver.
Keywords :
circuit simulation; code division multiple access; integrated circuit design; low-power electronics; radio receivers; spread spectrum communication; DSSS systems; WCDMA system; area efficient RAKE receiver; base stations; computed sub-symbols; direct sequence spread spectrum technique; mobile-stations; parallel de-spreader; power dissipation reduction; power efficient receiver; Clocks; Complexity theory; Computer architecture; Fading; Fingers; Hardware; Multiaccess communication; Multipath channels; Power dissipation; Spread spectrum communication;
Conference_Titel :
SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]
Print_ISBN :
0-7803-8182-3
DOI :
10.1109/SOC.2003.1241472
