HDL optimization using timed decision tables

Author

Li, Jian ; Gupta, Rajesh K.

Author_Institution

Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA

fYear

1996

fDate

3-7 Jun, 1996

Firstpage

51

Lastpage

54

Abstract

System-level presynthesis refers to the optimization of an input HDL description that produces an optimized HDL description suitable for subsequent synthesis tasks. In this paper, we present optimization of control flow in behavioral HDL descriptions using external Don´t Care conditions. The optimizations are carried out using a tabular model of system functionality, called Timed Decision Tables or TDTs. TDT based optimization presented here have been implemented in a program called PUMPKIN. Optimization results from several examples show a reduction of 3-88% in the size of synthesized hardware circuits depending upon the external Don´t Care information supplied by the user

Keywords

circuit optimisation; hardware description languages; high level synthesis; logic CAD; timing; HDL optimization; PUMPKIN; behavioral HDL descriptions; control flow; external Don´t Care conditions; input HDL description; synthesized hardware circuits; system functionality; system-level presynthesis; timed decision tables; Circuit synthesis; Computer languages; Computer science; Control system synthesis; Delay; Hardware design languages; Permission; Power system modeling; Testing; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference Proceedings 1996, 33rd

Conference_Location

Las Vegas, NV

ISSN

0738-100X

Print_ISBN

0-7803-3294-6

Type

conf

DOI

10.1109/DAC.1996.545544

Filename

545544