Title :
High-performance and low-voltage sense-amplifier techniques for sub-90nm SRAM
Author :
Sinha, Manoj ; Hsu, Steven ; Alvandpour, Atila ; Burleson, Wayne ; Krishnamurthy, Ram ; Borkar, Shekhar
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Abstract :
Large bit-line capacitance is one of the main bottlenecks to the performance of on-chip caches. New sense amplifier techniques need to explicitly address this challenge. This paper describes two sensing techniques to overcome this problem: a current sense amplifier (CSA) and a charge transfer sense amplifier (CTSA) and their implementation based on 90 nm CMOS technology. The current sense amplifier senses the cell current directly and shows a speed improvement of 17-20% for 128 memory cells as compared to the conventional voltage mode sense amplifier, for the same energy. The other is a charge transfer sense amplifier that takes advantage of large bit-line capacitance for its operation. The CTSA shows an improvement of 18-22% for read delay for 128 memory cells and consumes 15-18% less energy than the voltage mode sense amplifier. The CTSA results in reduced bit-line swing, which in turn leads to 30% lower bit-line energy than the conventional voltage mode.
Keywords :
CMOS memory circuits; SRAM chips; amplifiers; circuit simulation; integrated circuit design; low-power electronics; 90 nm; CMOS technology; CSA; CTSA; SRAM sense-amplifier; bit-line capacitance; bit-line swing reduction; charge transfer sense amplifier; current sense amplifier; high-performance sense-amplifier; low-voltage sense-amplifier; on-chip caches; read delay improvement; sensing speed improvement; CMOS technology; Capacitance; Charge transfer; Delay; Differential amplifiers; Integrated circuit interconnections; Microprocessors; Operational amplifiers; Random access memory; Voltage;
Conference_Titel :
SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]
Print_ISBN :
0-7803-8182-3
DOI :
10.1109/SOC.2003.1241474
