A low-complexity, high-speed Reed-Solomon decoder [fiber-optic communication system applications]

Author

Lee, Hanho ; Azam, Asad

Author_Institution

Dept. of Electr. & Comput. Eng., Connecticut Univ., Storrs, CT, USA

fYear

2003

fDate

17-20 Sept. 2003

Firstpage

127

Lastpage

130

Abstract

This paper presents a low-complexity, high-speed RS(255,239) decoder architecture, using a modified Euclidean (ME) algorithm, for high-speed fiber optic communication systems. The RS decoder features a low-complexity key equation solver using a novel pipelined recursive ME algorithm block. Pipelining allows inputs to be received at very high fiber optic rates and outputs to be delivered at correspondingly high rates with minimum delay. The recursive structure enables us to implement the low-complexity ME algorithm block. The low-complexity, high-speed RS decoder has been designed and implemented with 0.13 μm CMOS technology at a supply voltage of 1.1 V. It is suggested that the proposed RS decoder operates at a clock rate of 770 MHz and has a throughput of 6.16 Gb/s.

Keywords

CMOS logic circuits; Reed-Solomon codes; decoding; integrated circuit design; logic design; logic simulation; optical fibre communication; pipeline processing; 0.13 micron; 1.1 V; 6.16 Gbit/s; 770 MHz; CMOS RS decoder; RS239 decoder; RS255 decoder; high-speed Reed-Solomon decoder; high-speed fiber optic communication systems; low-complexity decoder; low-complexity key equation solver; modified Euclidean algorithm; pipelined recursive algorithm block; CMOS technology; Clocks; Decoding; Delay; Equations; Optical fiber communication; Optical fibers; Pipeline processing; Reed-Solomon codes; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]

Print_ISBN

0-7803-8182-3

Type

conf

DOI

10.1109/SOC.2003.1241477

Filename

1241477