Title :
MPEG-4 video bitstream structure analysis and its parsing architecture design
Author :
Chang, Hao-Chieh ; Chang, Yung-Chi ; Tsai, Yuan-Bin ; Fan, Chih-Peng ; Chen, Liang-Gee
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
In this paper, the hardware-oriented structure analysis and an efficient and flexible bitstream parser for MPEG-4 video are presented. The analysis of bitstream structure explores processing requirement and design constraint for bitstream-level processing. The proposed architecture is basically RAM-based that can be reconfigured for various applications. For high bitrate as about 40 Mbit/s, it needs only about 19 MIPS to parse the bitstream. The impact of the proposed architecture on MPEG-4 video is to enhance and extend the processing for bit domain translation and related real time applications
Keywords :
data compression; real-time systems; video coding; MPEG-4; bit domain translation; data compression; design constraint; parsing architecture design; processing requirement; real time applications; video bitstream structure analysis; Bit rate; Communication industry; Computer architecture; Decoding; Digital signal processing; Encoding; MPEG 4 Standard; Transform coding; Video coding; Video compression;
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
DOI :
10.1109/ISCAS.2000.856289
