CMOS differential circuits using charge-redistribution and reduced-swing schemes [logic circuits]

Author

Hong-Yi Huang ; Chou, Yung

Author_Institution

Dept. of Electron. Eng., Fu-Jen Catholic Univ., Taiwan

fYear

2003

fDate

17-20 Sept. 2003

Firstpage

147

Lastpage

150

Abstract

Charge-redistribution low-swing differential logic (CLDL) circuits, are presented in this work. This logic can implement a complex function in a single gate. The CLDL circuit utilizes a charge-redistribution and reduced-swing scheme to reduce the power dissipation. In addition, a pipeline structure is formed by a series connection structure controlled by a true-single-phase clock, thereby achieving high-speed operation. A pipelined multiplier-accumulator (MAC) and an 8 bit synchronous counter, using the CLDL structure, were designed in a standard 0.35 μm CMOS process.

Keywords

CMOS logic circuits; counting circuits; integrated circuit design; logic design; multiplying circuits; pipeline processing; 0.35 micron; 8 bit; CLDL circuits; CMOS differential logic circuits; MAC; charge-redistribution; low-swing differential logic; pipeline structure; pipelined multiplier-accumulator; power dissipation reduction; reduced-swing scheme; single gate complex functions; synchronous counter; true-single-phase clock; CMOS logic circuits; Clocks; Logic circuits; Logic functions; MOS devices; Pipelines; Power dissipation; Power engineering and energy; Signal generators; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]

Print_ISBN

0-7803-8182-3

Type

conf

DOI

10.1109/SOC.2003.1241481

Filename

1241481