A Multi-DSP Based Low-Latency Video Processing System

Author

Lei Dandan ; Jiang Hongxu ; Li Bo ; Ji Xiaonan

Author_Institution

Digital Media Lab., BUAA, Beijing, China

fYear

2009

fDate

26-28 Dec. 2009

Firstpage

1055

Lastpage

1058

Abstract

In this paper, a multi-DSP based low-latency video processing system is designed, in which one TMS320C6455 and one TMS320DM642 produced by TI are used as kernel processors. Several functions have been implemented, such as video deinterlacing and H.264 encoding. Not only could it have more uniform image quality, but also it greatly reduces the system latency. Considering the VLIW architecture and the memory resource limitation of TMS320C6000 DSPs, the paper optimizes the data storage and transfer respectively in order to reduce the processing latency and enhance the system´s performance; Moreover, by analysing the existing video-coding algorithm, a low latency video-coding algorithm structure is put forward to improve the inherent latency.

Keywords

digital signal processing chips; multiprocessing systems; operating system kernels; video coding; H.264 encoding; TMS320C6455; TMS320DM642; VLIW architecture; data storage; kernel processors; multi-DSP based low-latency video processing system; syetem latency; uniform image quality; video coding algorithm; video deinterlacing; Delay; Digital signal processing; Encoding; Image quality; Kernel; Memory architecture; Performance analysis; Process design; System performance; VLIW;

fLanguage

English

Publisher

ieee

Conference_Titel

Information Science and Engineering (ICISE), 2009 1st International Conference on

Conference_Location

Nanjing

Print_ISBN

978-1-4244-4909-5

Type

conf

DOI

10.1109/ICISE.2009.73

Filename

5455450