A low-jitter and low-power phase-locked loop design

Author

Chen, Kuo-Hsing ; Liao, Huan-Sen ; Tzou, Lin-Jiunn

Author_Institution

Dept. of Electr. Eng., Tamkang Univ., Tamsui, Taiwan

Volume

2

fYear

2000

fDate

2000

Firstpage

257

Abstract

This paper describes a design of digital phase-locked loop (DPLL), which has low-power consumption and low jitter features. A novel voltage controlled oscillator (VCO) and Phase-Frequency Detector (PFD) are proposed to reduce the total power consumption and phase error of the DPLL. The proposed VCO has low power consumption, and the PFD is a “three-state” structure with a dead zone of 5 ps. The power consumption of the proposed DPLL is lower than 6.7 mW, and the output-frequency range of the oscillator is from 200 MHz to 650 MHz. The worst-case cycle jitter is lower than 160 ps, and long-term jitter is lower than 220 ps. We confirm the results based on 0.5 μm CMOS technology and 3 V supply voltage

Keywords

CMOS digital integrated circuits; detector circuits; digital phase locked loops; integrated circuit design; jitter; low-power electronics; voltage-controlled oscillators; 0.5 micron; 200 to 650 MHz; 3 V; 6.7 mW; CMOS technology; DPLL; VCO; digital PLL; low-jitter PLL design; low-power PLL design; low-power consumption; phase error reduction; phase frequency detector; phase-locked loop design; voltage controlled oscillator; Delay effects; Energy consumption; Frequency conversion; Phase frequency detector; Phase locked loops; Short circuit currents; Switches; Variable structure systems; Voltage; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.856310

Filename

856310