ESD protection design for mixed-voltage-tolerant I/O buffers with substrate-triggered technique

Author

Ker, MingDou ; Hsu, HsinChyh

Author_Institution

Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2003

fDate

17-20 Sept. 2003

Firstpage

219

Lastpage

222

Abstract

A substrate-triggered technique is proposed to improve ESD protection efficiency of the stacked-NMOS device in a mixed-voltage I/O circuit. The substrate-triggered technique can further lower the trigger voltage of the stacked-NMOS device, to ensure effective ESD protection for the mixed-voltage I/O circuit. The proposed ESD protection circuit, with the substrate-triggered technique, for a 2.5 V/3.3 V tolerant mixed-voltage I/O circuit has been fabricated and verified in a 0.25 μm salicided CMOS process. Experimental results have confirmed that the HBM ESD robustness of the mixed-voltage I/O circuit can be increased ∼60% by this substrate-triggered design.

Keywords

CMOS integrated circuits; buffer circuits; electrostatic discharge; integrated circuit design; integrated circuit measurement; 0.25 micron; 2.5 V; 3.3 V; CMOS; ESD protection efficiency; HBM ESD robustness; mixed-voltage-tolerant I/O buffers; stacked-NMOS device; substrate-triggered technique; trigger voltage lowering; CMOS process; Circuits; Electrostatic discharge; MOS devices; MOSFETs; Power supplies; Protection; Robustness; Signal design; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]

Print_ISBN

0-7803-8182-3

Type

conf

DOI

10.1109/SOC.2003.1241496

Filename

1241496