Interconnect-driven multistage hierarchical floorplanning for soft modules

In this paper, we present a new multistage hierarchical floorplanning algorithm for soft modules integrated with fast but effective interconnect-driven module placement and hierarchical chip area minimization. The interconnect-driven module placement is achieved by using a fast cell-filling algorithm based on the interconnection relation of nets. Using the topology of module locations built by our cell-filling algorithm, a hierarchical chip area minimization algorithm, based on non-linear programming, is applied to minimize the total chip area. In addition, critical paths, or the connective strength of critical nets, could be easily enhanced during the step of analyzing interconnection relations for solving timing closure problems. Experimental results show that our multistage hierarchical approach can minimize chip area and total wire length simultaneously in a very efficient way.