Area minimization of clock distribution networks using local topology modification

The quality of the clock distribution networks (CDNs) impacts the performance of an SoC. In this paper, we propose local topology modification (LTM) in order to enhance the CDN´s quality in terms of total wire length and wire elongations. The incorporation of this method into a deferred-merge embedding algorithm (DME) and greedy-DME (GDME) reduces the total wire length by around 7.83% and 9.77% respectively, with a slight increase in run time. In addition, we show that GDME relies intensively on wire elongations and it offers a solution that suffers from high standard deviation of the path lengths between clock pins and the CDN´s root (SDPL). Applying LTM to GDME reduces wire elongations and SDPL by 96.4 % and 51.5 % respectively.