Analysis of soft error rate in flip-flops and scannable latches

Soft errors can be induced through radiation sources, with particles of low energy occurring far more frequently than particles of high energy. Therefore, smaller CMOS device are more easily affected by lower energy particles. Thus, soft errors are gaining importance as technology scales. Flip-flops, an important component of pipelined architectures, are becoming more susceptible to soft errors. This work analyzes soft error rates on a variety of flip-flops. The analysis was performed by implementing and simulating various designs in 70 nm, 1 V CMOS technology. First, we evaluate the critical charge for the susceptible nodes in each design. Further, we implement two hardening techniques and present the results. One attempts to increase the gate capacitance, the other improves the overall robustness of the circuit by replicating the master stage of the master-slave flip-flops, which leads to reduced power and area overhead.