Title :
Programmable de-skew clock generation based on dual digital delay-locked loop structure
Author_Institution :
Intel Corp., Chandler, AZ, USA
Abstract :
A DSP-based fully digital programmable de-skew clock generation circuit for a computer I/O interface is presented. A 32-delay programmable 4-port de-skew clock generation circuit for a 133 MHz SDRAM interface was developed using a 0.25 μm standard CMOS process technology. It occupies an area of 400 μm×300 μm and consumes about 4 mW of power with a skew control accuracy of ±125 ps.
Keywords :
CMOS digital integrated circuits; clocks; computer interfaces; delay lock loops; digital signal processing chips; integrated circuit design; 0.25 micron; 133 MHz; 300 micron; 4 mW; 400 micron; CMOS; DSP-based clock generation; SDRAM interface; computer I/O interface; delay locked loop; digital programmable de-skew clock generation circuit; dual digital DLL structure; multiport clock generation circuit; skew control accuracy; Circuits; Clocks; Delay; Detectors; Digital filters; Feedback loop; Low pass filters; Master-slave; Phase detection; Synchronous generators;
Conference_Titel :
SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]
Print_ISBN :
0-7803-8182-3
DOI :
10.1109/SOC.2003.1241505
