DocumentCode
2231259
Title
A low-voltage loadless 4N SRAM with smart hidden refresh
Author
Huang, Hong-Yi ; Yen, Tzu-Sung
Author_Institution
Dept. of Electron. Eng., Fu-Jen Catholic Univ., Taiwan
fYear
2003
fDate
17-20 Sept. 2003
Firstpage
251
Lastpage
252
Abstract
This work describes a smart hidden refresh scheme for designing embedded 4N SRAM. An improved dynamic NOR decoder is also presented to achieve high-speed and low-power operation at low supply voltage. The smart refresh scheme can overcome the performance limitations of the conventional hidden refresh scheme. The new design has the same I/O specification as that of 6T SRAM. It can be fabricated in standard CMOS processes as a small-area embedded memory. A test chip of 256×8 cells performs at 77 MHz at a supply voltage of 1.2 V. The area is 25% less than that of the 6T SRAM.
Keywords
CMOS memory circuits; SRAM chips; integrated circuit design; low-power electronics; 1.2 V; 2048 bit; 77 MHz; 8 bit; CMOS small-area embedded memory; dynamic NOR decoder; loadless 4N SRAM; low-power operation; low-voltage SRAM; smart hidden refresh; CMOS process; Circuits; Clocks; Decoding; Design engineering; Leakage current; MOSFETs; Random access memory; Timing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]
Print_ISBN
0-7803-8182-3
Type
conf
DOI
10.1109/SOC.2003.1241506
Filename
1241506
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