Synchrony detection for spike-mediated computation

We present a novel architecture for detecting spatiotemporal synchrony among pulse trains. This is useful for performing meaningful computation in a system where analog information is conveyed via the precise timing of spikes in addition to the mean spike rate-without explicitly leaving the spike domain. Using a resistive network to restrict the spatial extent of the window of meaningful synchrony, and an array of pseudo-AFGAs to restrict the temporal extent of the window, we are able to perform the synchrony detection task in continous time, without sampling. We have implemented this architecture using only 10 transistors per spatial channel, and have fabricated three 32-node linear arrays using a 1.2 μ CMOS process. We present experimental results