Title :
A hierarchical partitioning algorithm for VLSI designs
Author :
Wen Chen Huang ; Wang, Jyh-Herng ; Chien-Ming Huang ; Chi, Mely Chen
Author_Institution :
Dept. of Inf. & Comput. Eng., Chung Yuan Christian Univ., Chung Li, Taiwan
Abstract :
A hierarchical partitioning algorithm (HPA) partitions a circuit to several physical blocks while maintaining the logical hierarchy of the circuit. It uses a cost function which combines the net-cut, path-weight, and area of each module. A dynamic programming-based approach is utilized to find the minimal cost for different numbers of partitions. The area constraint helps the HPA to obtain area-balanced partitioning results in a shorter CPU time. The program has been tested on several industrial circuits. Experimental results are presented.
Keywords :
VLSI; dynamic programming; integrated circuit design; logic partitioning; HPA; VLSI design; area-balanced partitioning; circuit logical hierarchy; cost function; dynamic programming; hierarchical partitioning algorithm; module area constraint; module net-cut; module path-weight; partition minimal cost; Algorithm design and analysis; Central Processing Unit; Circuit testing; Cost function; Delay; Equations; Field programmable gate arrays; Maintenance engineering; Partitioning algorithms; Very large scale integration;
Conference_Titel :
SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]
Print_ISBN :
0-7803-8182-3
DOI :
10.1109/SOC.2003.1241513
