Efficient bit-oriented implementation of FIR filter using a new compressor

In this paper, we present a bit-oriented architecture for the digital finite impulse response (FIR) filter with adaptive coefficients. Instead of using multipliers, the FIR operation is regarded as the summation of a larger number of operands. Our architecture utilizes a new compressor called the six-to-triple compressor, which converts six data bits of equal weights into a triple-digit representation. Using such a compressor as the basic building block, an FIR can be implemented as an efficient and regular structure that lends itself to automation. Experiments show that the proposed architecture could achieve a 28.4 % reduction on the area-delay product as compared to the traditional high-speed transposed form for an FIR design.