DocumentCode
2231702
Title
Asynchronous transfer mode cell delineator implementations
Author
Griffith, G.E. ; Arslan, T. ; Erdogan, A.T.
Author_Institution
Inst. for Syst. Level Integration, Livingston, UK
fYear
2003
fDate
17-20 Sept. 2003
Firstpage
289
Lastpage
292
Abstract
Several algorithms for performing cell delineation on a bit-serial and octet-parallel basis are considered. Four algorithms were implemented in total, two bit-serial and two octet-parallel, for the design of cell delineators through to netlist generation. Analysis is provided for post-synthesis designs detailing speed, area and power parameters for each implementation at an input data rate of 160 Mbps and 1280 Mbps.
Keywords
asynchronous transfer mode; logic design; logic simulation; packet switching; 1280 Mbit/s; 160 Mbit/s; ATM cell delineator implementations; asynchronous transfer mode; bit-serial algorithms; cell switched networks; input data rate; octet-parallel algorithms; octet-parallel moving window polynomial divider circuit; packet-switching techniques; Algorithm design and analysis; Asynchronous transfer mode; Error correction; Packet switching; Payloads; Physical layer; Routing; Telecommunication traffic; Time division multiplexing; Transportation;
fLanguage
English
Publisher
ieee
Conference_Titel
SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]
Print_ISBN
0-7803-8182-3
Type
conf
DOI
10.1109/SOC.2003.1241525
Filename
1241525
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