Title :
VHDLStyler - a script-based tool for IP design modification [SoC design]
Author :
Biichner, T. ; Smith, Christopher
Author_Institution :
IBM Deutschland Entwicklung GmbH, Boblingen, Germany
Abstract :
This paper describes a method to enable the transition from a given design environment to a modern SoC design flow at minimal cost, and with increased productivity for future designs. A Java-based tool is presented that allows the script-based modification of existing VHDL code for a wide range of applications.
Keywords :
Java; hardware description languages; industrial property; logic CAD; system-on-chip; IP design modification; Java-based tool; SoC design flow; VHDL code transition; VHDLStyler; script-based design modification tool; Convergence; Costs; Design engineering; Design methodology; Documentation; Hardware design languages; Information analysis; Java; Productivity; Writing;
Conference_Titel :
SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]
Print_ISBN :
0-7803-8182-3
DOI :
10.1109/SOC.2003.1241529
