Title :
Synthesis of NoC Interconnects for Custom MPSoC Architectures
Author :
Khan, Gul N. ; Tino, Anita
Author_Institution :
Electr. & Comput. Eng., Ryerson Univ., Toronto, ON, Canada
Abstract :
As technology continues to demand high performance, low power, and integration density, NoC system designers consider multiple aspects during the design phase. This paper addresses these issues and presents an NoC design methodology for generating high quality interconnects for custom Multiprocessor System-on-Chip (MPSoC) architectures. Our design methodology incorporates the main objectives of power and performance during topology synthesis while employing both analytical and simulation based automated techniques. A rendezvous interaction performance analysis method is presented where Layered Queuing Network models are invoked to observe the asynchronous interactions between NoC components and identify possible performance degradation in the on-chip network. Several experiments are conducted using various SoC benchmark applications to compare the power and performance outcomes of our proposed technique.
Keywords :
integrated circuit interconnections; multiprocessing systems; network topology; network-on-chip; MPSoC architectures; NoC interconnects; integration density; layered queuing network models; multiprocessor system-on-chip; network-on-chip; rendezvous interaction performance analysis; topology synthesis; Analytical models; Delay; Generators; Network topology; System recovery; System-on-a-chip; Topology; MPSoCs; NoC architectures; Power and Performance efficiency; Topology Synthesis;
Conference_Titel :
Networks on Chip (NoCS), 2012 Sixth IEEE/ACM International Symposium on
Conference_Location :
Copenhagen
Print_ISBN :
978-1-4673-0973-8
DOI :
10.1109/NOCS.2012.16