A low-jitter mutual-correlated pulsewidth control loop circuit

Author

Lin, Wei-Ming ; Huang, Hong-Yi

fYear

2003

fDate

17-20 Sept. 2003

Firstpage

301

Lastpage

304

Abstract

This work presents a low-jitter pulsewidth control loop (PWCL) circuit. A mutual-correlated scheme is implemented to adjust the duty cycle and increase the stability of the PWCL. The design is less sensitive to process variation. The jitter induced by voltage ripple is suppressed. The circuit is implemented using 0.35 μm IP4M CMOS process. The area of the PWCL is 136×143 μm². At an operating frequency of 300 MHz, the power dissipation and voltage ripple are reduced by 35.4% and 93.7%, respectively. A test chip is successfully verified to obtain 42 ps jitter at an operating frequency of 900 MHz.

Keywords

CMOS integrated circuits; circuit stability; clocks; integrated circuit design; phase locked loops; phase locked oscillators; pulse generators; timing jitter; 0.35 micron; 136 micron; 143 micron; 300 MHz; 900 MHz; CMOS; PLL; PWCL stability; duty cycle control; low-jitter pulsewidth control circuit; mutual-correlated pulsewidth control loop circuit; phase-locked loop; voltage ripple jitter; Charge pumps; Delay; Frequency conversion; Jitter; Oscillators; Phase locked loops; Pulse circuits; Space vector pulse width modulation; Virtual colonoscopy; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]

Print_ISBN

0-7803-8182-3

Type

conf

DOI

10.1109/SOC.2003.1241530

Filename

1241530