Title :
SiGe BiCMOS PAM-4 clock and data recovery circuit for high-speed serial communications
Author :
Hsieh, Mingta ; Sobelman, Gerald E.
Author_Institution :
Dept. of Electr. & Comput. Eng., Minnesota Univ., USA
Abstract :
A multilevel clock and data recovery (CDR) circuit for highspeed serial data transmission was designed using the IBM 6 HP 0.25 μm SiGe BiCMOS process technology. The circuit extracts the clock from a 32 Gb/s 4-level pulse amplitude modulated (PAM-4) input signal and outputs four channels of retimed NRZ data at 8 Gb/s per channel. The CDR design incorporates a PAM-4 to 2-bit-binary converter, a phase/frequency detector, a loop filter, a quadrature LC ring oscillator and a data-retiming module. The circuit operates using a 3.3 V supply voltage with a 350 mA current consumption. The simulation results show that the peak-to-peak jitter is 1.3 ps, the capture range is 2 GHz, the acquisition time is 200 ns and the input sensitivity is 150 mV. This PAM-based CDR technique is quite suitable for low-loss transmission channels such as fiber optic communications or short-distance copper links, including network-on-chip (NOC) implementations and storage area networks (SANs).
Keywords :
BiCMOS integrated circuits; Ge-Si alloys; circuit simulation; convertors; data communication equipment; integrated circuit design; network interfaces; optical fibre communication; phase detectors; pulse amplitude modulation; semiconductor materials; storage area networks; synchronisation; timing jitter; 0.25 micron; 150 mV; 200 ns; 3.3 V; 32 Gbit/s; 350 mA; 8 Gbit/s; NOC; PAM-4 clock/data recovery circuit; SAN; SiGe; SiGe BiCMOS clock/data recovery circuit; acquisition time; binary converter; capture range; clock extraction; data-retiming module; fiber optic communications; high-speed serial communications; loop filter; low-loss transmission channels; multilevel CDR circuit; network-on-chip; peak-to-peak jitter; phase/frequency detector; pulse amplitude modulated input signal; quadrature LC ring oscillator; retimed NRZ data; short-distance copper links; storage area networks; Amplitude modulation; BiCMOS integrated circuits; Clocks; Data communication; Data mining; Germanium silicon alloys; Network-on-a-chip; Pulse circuits; Pulse modulation; Silicon germanium;
Conference_Titel :
SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]
Print_ISBN :
0-7803-8182-3
DOI :
10.1109/SOC.2003.1241531
