A UTMI-compatible physical-layer USB2.0 transceiver chip

A physical layer (PHY) USB2.0 transceiver chip was designed and fabricated by using a 0.25 μm CMOS technology. The PHY chip is compatible with the USB2.0 transceiver macrocell interface (UTMI) specification. It has a 16 bit parallel interface to its link layer. The electrical tests on the fabricated chip confirmed the successful operation of analog circuitry such as the clock data recovery (CDR) circuit, the output drivers, and the receiver circuits for both high-speed (480 Mbps) and full-speed (12 Mbps) data transmissions. The BERs were measured to be less than 1E^-12 for both data transmissions. Functional verifications for USB2.0 protocol by using a logic analyzer with a pattern generator showed the successful operations of digital circuitry such as the bit stuffer/un-stuffer and the NRZI encoder/decoder. The chip area, excluding the IO pads, was 0.91×1.82 mm². The power consumption at a supply voltage of 2.5 V was 225 mW and 150 mW, for high-speed and full-speed operations, respectively.