• DocumentCode
    2231859
  • Title

    Packet processing with blocking for bursty traffic on multi-thread network processor

  • Author

    Chang, Yeim-Kuan ; Kuo, Fang-Chen

  • Author_Institution
    Dept. of Comput. Sci. & Inf. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
  • fYear
    2009
  • fDate
    22-24 June 2009
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    It is well-known that there are bursty accesses in network traffic. It means a burst of packets with the same meaningful headers are usually received by routers at the same time. With such traffic, routers usually perform the same computations and access the same memory location repeatedly. To utilize this characteristic of network traffic, many cache schemes are proposed to deal with the bursty access patterns. However, in the multi-thread network processor based routers, the existing cache schemes will not suit to the bursty traffic. Since all threads may all deal with the packets with the same headers, if the former threads do not update the cache entries yet, the subsequent threads still have to repeat the computations due to the cache miss. In this paper, we propose a cache scheme called B-cache for the multi-thread network processors. B-cache blocks the subsequent threads from doing the same computations which are being processed by the former thread. By applying B-cache, any packet processing tasks with high locality characteristic, such as IP address lookup, packet classification, and intrusion detection, can avoid the duplicate computations and hence achieve a better packet processing rate. We implement the proposed B-cache scheme on Intel IXP2400 network processor, the experimental results shows that our B-cache scheme can achieves the line speed of Intel IXP2400.
  • Keywords
    cache storage; multi-threading; multiprocessing systems; telecommunication traffic; B-cache scheme; Intel IXP2400 network processor; bursty network traffic; multithread network processor; network router; packet processing; Telecommunication traffic; Intel IXP2400; cache; multi-thread; network processor;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Switching and Routing, 2009. HPSR 2009. International Conference on
  • Conference_Location
    Paris
  • Print_ISBN
    978-1-4244-5174-6
  • Electronic_ISBN
    978-1-4244-5174-6
  • Type

    conf

  • DOI
    10.1109/HPSR.2009.5307419
  • Filename
    5307419