Low-voltage class AB two-step sampling switched-currents

Author

Worapishet, Apisak ; Hughes, John B. ; Toumazou, Chris

Author_Institution

Mahanakorn Univ. of Technol., Bangkok, Thailand

Volume

2

fYear

2000

fDate

2000

Firstpage

413

Abstract

The feasibility of extending a class AB SI configuration to two-step sampling switched-currents is demonstrated. Particular emphasis is given to observing its practical benefits and possibility of reducing supply voltage requirement in comparison to class A S²I. As indicated by both theoretical analysis and simulations of memory cells, the use of class AB techniques can enable S²I circuits to operate at a lower supply voltage (as low as 2.4 V for a 5 V CMOS process with V_t=0.8 V) while exhibiting approximately 3.5 times figure-of-merit improvement (including SNR, speed and power) over the conventional class A S²I approach

Keywords

CMOS analogue integrated circuits; low-power electronics; sample and hold circuits; switched current circuits; 2.4 V; S²I circuits; class AB SI configuration; figure-of-merit improvement; supply voltage requirement; two-step sampling switched-currents; CMOS process; Circuit simulation; Current supplies; Ear; Educational institutions; Laboratories; Low voltage; MOS devices; Sampling methods; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.856352

Filename

856352