Optimization of an MPEG-4 decoding algorithm on a “very long instruction word” architecture

The paper presents the optimization of a software MPEG-4 video decoder on a specific architecture, suitable for parallel processing. First, a simplified structure of an MPEG-4 video decoder is reviewed. Second, a processor architecture that exploits the intrinsic parallelism of a video-decoding algorithm (architecture based on the concept of the “very long instruction word” machine) is presented. Then, the techniques used to write efficient C code for the VLIW machine and the principles on which these techniques are based are discussed. Finally, the paper presents the results obtained applying the optimization techniques to an MPEG-4 video decoder and a comparison between the performance obtained with the VLIW (250 MHz) processor and with a superscalar Pentium II (266 MHz) processor