DocumentCode
2232153
Title
An architecture for MPEG-4 binary shape decoder
Author
Thinakaran, J. ; Ho, Duan-Juat ; Ling, Nam
Author_Institution
Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore
Volume
2
fYear
2000
fDate
2000
Firstpage
457
Abstract
An architecture for MPEG-4 binary shape decoder is presented. Our novel techniques include a look-ahead unit to speed up the probability generation process, the usage of synchronous ROM for reduced power consumption, and the use of simple shift registers instead of large barrel shifters to reduce the area of the decoder. The decoder architecture is designed using VHDL. The decoder is able to decode up to 100 Mbits/s and can be used to achieve Main Profile at Level Three performance requirement
Keywords
arithmetic codes; decoding; digital arithmetic; hardware description languages; probability; shift registers; video signal processing; MPEG-4; Main Profile at Level Three performance requirement; VHDL; binary shape decoder; look-ahead unit; power consumption; probability generation process; shift registers; synchronous ROM; Arithmetic; Computer aided engineering; Decoding; Encoding; Energy consumption; MPEG 4 Standard; Read only memory; Shape; Signal processing algorithms; Synchronous generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location
Geneva
Print_ISBN
0-7803-5482-6
Type
conf
DOI
10.1109/ISCAS.2000.856363
Filename
856363
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