Title :
Design of nanometer scale CMOS circuits
Author_Institution :
Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
Summary form only given. The tremendous growth of the semiconductor industry is fueled by scaling of technology following Moore´s law. However, as we enter the nanometer regime, leakage current is becoming one of the main concerns for designers. The circuit designers have to work hand in hand with device designers to deliver high-performance yet low-power and noise-tolerant systems. This talk considers different leakage mechanisms in nanometer scale devices and propose device architecture and circuit/CAD solutions for leakage-tolerant logic and memories for scaled technologies.
Keywords :
CMOS digital integrated circuits; CMOS memory circuits; integrated circuit design; integrated circuit noise; leakage currents; logic design; low-power electronics; nanoelectronics; device architecture; leakage current; leakage-tolerant logic; leakage-tolerant memories; low-power systems; nanometer scale CMOS circuits; nanometer scale device leakage mechanisms; noise-tolerant systems; technology scaling; CMOS technology; Circuit noise; Design automation; Electronics industry; Leakage current; Logic design; Logic devices; Moore´s Law; Nanoscale devices; Semiconductor device noise;
Conference_Titel :
SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]
Print_ISBN :
0-7803-8182-3
DOI :
10.1109/SOC.2003.1241560
