Title :
Design and implementation of surfing scheme to wave pipelined differential serial interconnect
Author :
Bhaskar, M. ; Parthiban, D. ; Venkataramani, B.
Author_Institution :
Dept. of ECE, Nat. Inst. of Technol., Tiruchirappalli, India
Abstract :
In literature, surfing scheme has been used in wave pipelined serial interconnects to decrease the delay and ensure transmission reliability. In this paper, a “Controllable inverter pair” is proposed for surfing the differential wave pipelined serial interconnects. The proposed surfing scheme is implemented in UMC 0.18μm technology and the post layout performance is studied through simulation in Cadence spectre tool. The performance of the new scheme is compared with that of a single ended wave-pipelined link with surfing. The proposed scheme permits the data transmission rate of 2.78Gbps and it is higher by a factor of 2.08 compared to the single ended scheme. It also does not require any set up time constraints unlike single ended scheme, where the surfing signal must be ascertained before the data signal about one fourth of the data period.
Keywords :
integrated circuit interconnections; logic gates; Cadence spectre tool; UMC 0.18μm technology; controllable inverter pair; data transmission; single ended wave-pipelined link; size 0.18 mum; surfing scheme; surfing signal; transmission reliability; wave pipelined differential serial interconnect; Data communication; Delay; Integrated circuit interconnections; Inverters; Jitter; Layout; Pipeline processing; Controllable inverter pair; Wave pipelining; differential serial interconnect link; surfing;
Conference_Titel :
Recent Advances in Intelligent Computational Systems (RAICS), 2011 IEEE
Conference_Location :
Trivandrum
Print_ISBN :
978-1-4244-9478-1
DOI :
10.1109/RAICS.2011.6069308
