A 0.8 V switched-opamp bandpass ΔΣ modulator using a two-path architecture

Author

Chang, Hsiang-Hui ; Chen, Shang-Ping ; Cheng, Kuang-Wei ; Liu, Shen-Iuan

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

2002

fDate

2002

Firstpage

1

Lastpage

4

Abstract

In this paper, a very low-voltage fourth-order bandpass delta-sigma modulator with a two-path architecture is presented. Using the modified switched opamp technique enables the modulator to operate at only 0.8 V supply voltage without any voltage multiplier or bootstrapping switch. Realized in a 0.25 μm 1P5M standard CMOS process, the prototype modulator exhibits a signal-to-noise-plus-distortion ratio (SNDR) of 60.6 db and a dynamic range (DR) of 68 db in a 30 kHz signal bandwidth centered at 1.25 MHz while consuming 2.5 mW and occupying an active area of 2.11 mm².

Keywords

CMOS integrated circuits; delta-sigma modulation; integrated circuit design; integrated circuit measurement; low-power electronics; operational amplifiers; 0.25 micron; 0.8 V; 1.25 MHz; 2.5 mW; 30 kHz; CMOS process; CMOS switched-opamp bandpass delta-sigma modulator; DR; SNDR; bandpass A/D converters; bootstrapping switches; dynamic range; modulator dual-path architecture; modulator power consumption/active area; modulator supply voltage; signal bandwidth center frequency; signal to noise plus distortion ratio; switched opamp techniques; very low-voltage fourth-order bandpass delta-sigma modulator; voltage multipliers; Band pass filters; Clocks; Delta modulation; Feedback circuits; Low voltage; Sampling methods; Signal processing; Switching circuits; Transfer functions; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-7363-4

Type

conf

DOI

10.1109/APASIC.2002.1031517

Filename

1031517