A new low-voltage CMOS 1-bit full adder for high performance applications

Author

Wey, I-Chyn ; Huang, Chun-Hua ; Chow, Hwang-Chemg

Author_Institution

Dept. of Electron. Eng., Chang Gung Univ., Tao-Yuan, Taiwan

fYear

2002

fDate

2002

Firstpage

21

Lastpage

24

Abstract

In this paper, a new low-voltage high-performance CMOS 1-bit full adder circuit is proposed. The new design is derived by combining XOR (XNOR) gates, used in the conventional full adder, and transmission gates. The proposed full adder can provide full voltage swing at a low supply voltage and offers superior performance in both power and speed than the conventional full adder, the transmission full adder, and the low-voltage full adder. Based on the simulation results performed by HSPICE, the new low-voltage design consumes minimal power and has a minimal power-delay product in the TSMC 0.35 μm process, as supply voltage varies from 3.3 V to 2 V. Also, the new cell is demonstrated to consume minimal power as adopted in a 4×4 bit carry-save array adder, and a 4×4 bit pipelined carry-save array adder.

Keywords

CMOS logic circuits; SPICE; adders; carry logic; circuit simulation; integrated circuit design; integrated circuit modelling; logic CAD; logic gates; logic simulation; low-power electronics; 0.35 micron; 1 bit; 2 to 3.3 V; CMOS low-voltage single-bit full adders; HSPICE simulations; XNOR gates; XOR gates; high performance applications; low supply voltage full voltage swing; minimal power consumption; minimal power-delay product; pipelined carry-save array adders; power/speed performance; transmission full adders; transmission gates; Adders; Batteries; CMOS technology; Circuit synthesis; Digital signal processing; Energy consumption; Low voltage; Power dissipation; Power supplies; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-7363-4

Type

conf

DOI

10.1109/APASIC.2002.1031522

Filename

1031522