Schematic driven module generation for analog circuits with performance optimization and matching considerations

A technology independent correct-by-construction module generation for analog circuits is described. The designer selects an arbitrary analog circuit partition in the schematic, and the procedure generates the corresponding layout as a optimal stack of transistors with complete intra-module connectivity. The matching requirements are used as the primary constraint along with considerations for parasitics, aspect-ratio, and area. For each of the modules, the port structures are also created for simplified routing. Corresponding to the selected circuit partition, a fully parameterized design rule independent module is generated. Any changes in the schematic and the design rules are automatically reflected in each of the modules. Results are demonstrated through a test chip