Title :
A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme
Author :
Hamada, Mototsugu ; Takahashi, Masafumi ; Arakida, Hideho ; Chiba, Akihiko ; Terazawa, Toshihiro ; Ishikawa, Takashi ; Kanazawa, Masahiro ; Igarashi, Mutsunori ; Usami, Kimiyoshi ; Kuroda, Tadahiro
Author_Institution :
Syst. ULSI Eng. Lab., Toshiba Corp., Kawasaki, Japan
Abstract :
A novel design technique which combines a variable supply-voltage scheme and a clustered voltage scaling is presented (VS-CVS scheme). A theory to choose the optimum supply voltages in the VS-CVS scheme is discussed which enables us to perform chip design in a top-down fashion. Level-shifting flip-flops are developed which reduce power, delay and area penalties significantly. Application of this technique to an MPEG4 video codec saves 55% of the power dissipation without degrading circuit performance compared to a conventional CMOS design
Keywords :
CMOS digital integrated circuits; delays; flip-flops; integrated circuit design; logic CAD; low-power electronics; CMOS design; MPEG4 video codec; VS-CVS scheme; area penalties; chip design; clustered voltage scaling; delay; level-shifting flip-flops; power dissipation; top-down low-power design technique; variable supply-voltage scheme; Chip scale packaging; Circuit optimization; Circuit synthesis; Degradation; Delay; Energy consumption; Flip-flops; Frequency; Power supplies; Voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-4292-5
DOI :
10.1109/CICC.1998.695026
