A 1.3 V low-power 430 MHz front-end using a standard digital CMOS process [ISM wireless link]

Author

Melly, T. ; Porret, A.-S. ; Enz, C.C. ; Kayal, M.

Author_Institution

Electron. Lab., Fed. Inst. of Technol., Lausanne, Switzerland

fYear

1998

fDate

11-14 May 1998

Firstpage

503

Lastpage

506

Abstract

A low-power and low-voltage (LP/LV) RF front-end operating at 430 MHz and implemented in a standard 0.5 μm digital CMOS process is described. Specific LP/LV bias techniques and design tradeoffs are discussed and their application to the design of a fully integrated direct-conversion receiver is presented. The RF building blocks including a 200 μA LNA, two different 50 μA mixers and a ring-oscillator with differential I-Q outputs consuming 300 μA at 430 MHz, have been manufactured and their performances measured. Taking into account the severe power budget, a total double sideband (DSB) noise figure of 17 dB was achieved, together with a spurious free dynamic range of 55 dB at 60 kHz bandwidth, which is sufficient for the targeted application

Keywords

UHF integrated circuits; VLSI; integrated circuit design; low-power electronics; mixed analogue-digital integrated circuits; radio data systems; radio links; transceivers; 0.5 micron; 1.3 V; 17 dB; 200 muA; 300 muA; 430 MHz; 50 muA; 60 kHz; ISM wireless link; LNA; LP/LV bias techniques; RF front-end; design tradeoffs; differential I-Q outputs; direct-conversion receiver; double sideband noise figure; low-power electronics; power budget; ring-oscillator; spurious free dynamic range; standard digital CMOS process; 1f noise; Bandwidth; CMOS process; CMOS technology; Dynamic range; Energy consumption; Frequency shift keying; Noise figure; Radio frequency; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-4292-5

Type

conf

DOI

10.1109/CICC.1998.695028

Filename

695028