A 2.5 Gbps CMOS data serializer

Author

Wong, Meng-Tzer ; Chen, Wei-Zen

Author_Institution

Dept. of Electr. Eng., Nat. Central Univ., Chung-li, Taiwan

fYear

2002

fDate

2002

Firstpage

73

Lastpage

76

Abstract

This paper describes the design of a 2.5 Gbps CMOS data serializer, including a low jitter multiphase phase-locked loop, a multiplexer, and an output buffer. High speed parallel to serial data conversion is toggled by the multiphase PLL. This serializer achieves a conversion rate of up to 312.5 Mbyte/s and a transmission speed of 2.5 Gbps. The measured RMS jitter is less than 6 ps from a 2.5 Gbps data output. The measured eye diagram meets OC-48 transition mask. Die size is 1062 μm×1020 μm.

Keywords

CMOS integrated circuits; binary sequences; buffer circuits; data communication equipment; high-speed integrated circuits; integrated circuit design; integrated circuit measurement; jitter; multiplexing equipment; optical transmitters; phase locked loops; 1020 micron; 1062 micron; 2.5 Gbit/s; 312.5 Mbyte/s; CMOS data serializer design; OC-48 transition mask; PISO; RMS jitter; conversion rate; data output; die size; eye diagram; high speed parallel to serial data conversion; laser driver; low jitter multiphase phase-locked loop; multiphase PLL; multiplexer; optical transmitters; output buffer; parallel-in-serial-out; transmission speed; Bandwidth; Circuit noise; Data conversion; Delay; Frequency conversion; Jitter; Multiplexing; Phase frequency detector; Phase locked loops; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-7363-4

Type

conf

DOI

10.1109/APASIC.2002.1031535

Filename

1031535