A high-performance circuit technique for CMOS dynamic logic

Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CMOS inverter at the output of dynamic node which is more noise immune and has less capacitance at the output node. In this paper we have proposed a novel circuit for domino logic which is more noise robust and has very less power-delay product (PDP) as compared to previous reported articles. Low PDP is achieved by reducing the short circuit current during evaluation phase when PDN is conducting and also the leakage current when PDN is not conducting.